In digital systems, a common technique for transferring binary data between first and second elements of the digital system is to serialize the data and shift it one bit at a time onto a message interface line interconnecting the first and second elements. In most arrangements of this type, the message interface line does not transfer information as to the rate at which the transmitting element is shifting data bits onto the message line. Since the receiving element cannot decipher the transferred information without this rate information, both transmitting and receiving elements normally have access to a clock which is utilized by both transmitting and receiving elements to define the message bit rate on the message interface line. The clock may be supplied by the transmitting element, the receiving element or, in situations characterized by slow message rates and short message lengths, it may be generated separately by both the transmitting and receiving elements.
In a typical digital system, the transmission frequency of the data signal and (any) clock signal is not measurably affected by the length of the interface line or the number or type of intervening system elements between the transmitting and receiving elements. However, the length of the interface line and the presence of intervening system elements does introduce significant transmission delays between the transmitting and receiving elements. The magnitude of this delay can be many multiples of the message rate period, and its precise values for all systems built to identical design specifications may not be quantifiable by the designer with better resolution than a significant fraction of, or even multiples of, the message rate period. Thus, even in the most simple system where the transmitting element transmits data and clock information to the receiving element on separate interface lines, the difference between the delays of the data and clock signals may not be quantifiable with better resolution than previously stated. The effect of these delays is that while the clock signal can be reliably used to indicate the frequency with which data bits appear on the message interface line, it provides insufficient (or no) information regarding the points at which one data bit ends and the next begins; viz, no phase information is available.
In many digital data communication systems, it is desirous to be able to utilize the clock signal to strobe the received data into a flip-flop which may, for example, be the first element of a shift register. Typically this flip-flop responds to one edge of the clock. Thus, for example, the flip-flop may respond to the clock's transition from a low to a high level by latching the data signal presented to its input. Those skilled in the art will appreciate that a typical flip-flop will not respond predictably if its data input is changing state during a small time interval on either side of the active (or used) edge of the clock. These time intervals on either side of the clock, known as setup and hold times, are graphically illustrated in FIG. 1A. Thus, when the active edges of the clock occur sufficiently far from the data transitions (as defined by T.sub.SETUP and T.sub.HOLD) as in the case for CLOCK-1 in FIG. 1B, the flip-flop's output reliably reproduces the message, as can be seen from the DATA-OUT waveform. To the contrary, if the CLOCK-2 signal shown in FIG. 1B was used to strobe DATA-IN, the DATA-OUT values produced might not reliably reproduce the message since the active edges of CLOCK-2 are nearly coincident with the DATA-IN transitions.
With the latter discussion in mind, those skilled in the art will readily appreciate how the above described clocking condition manifests itself in a data communications system. Thus, in a typical data communications system, a receiving element (or receiver) receives a clock signal of the same frequency as the received data, but with arbitrary phase relationship to the received data. In addition, the beginning of each message typically consists of a known, specified pattern on the data line which is utilized to frame the message. Thus, for example, many existing message protocols start with the transition from the quiescent (or no message) state of the data interface line to the alternate state, for one or more message bit times known as mark bits. These mark bits contain no message information, but instead indicate that the subsequent n-bits received constitute a message. As an alternative to the use of mark bits, the system protocol may be specified so that each time it is necessary to generate the proper clock, a special message with no other purpose but to provide framing information is sent to the receiving element. Upon receipt of the framing signal, it is the job of the receiver to generate a clock signal of the same frequency as the received clock signal, but one that will insure that the phase relationship to the received data is such that active clock edges occur sufficiently far from data transitions to allow for reliable strobing of the data signals.
In the prior art, multiple techniques for insuring that the clock signals are in proper phase with respect to the data signals have been utilized.
One of such prior art techniques, typically employed in asynchronous datacom systems, uses a clock with a frequency which is a multiple of the message's (data) frequency to sample the incoming data signal at the higher clock frequency. The multiplicity of samples per data bit allows the samples at the edge of the data cells to be incorrect, while the center of the data cell can be reliably detected and sampled. This technique also tolerates variations in the frequencies of the clock and data since the sampling clock frequency is not required to be a precise mutiple of the data frequency. This technique is thus applicable to the previously discussed configuration wherein the clock signal is generated separately by both transmitter and receiver. The drawback of this technique is in the requirement of the higher frequency clock, which in a typical asynchronous datacom system is eight or sixteen times the data frequency. Because of this requirement, the clock may be impractical to generate for high data frequencies.
A second prior art solution to the problem, presently utilized in synchronous datacom systems, is to limit the message frequency, in combination with the length (and therefore the delay) of the interface path between transmitter and receiver, such that the clock/data skew is never large enough to move the active edge of the clock signal to a point too close to the edge of the data cell. The obvious disadvantage of this technique is that it limits either the data rate or the length of the interface, or both. This disadvantage may be partially overcome by utilizing repeater stations close enough together to satisfy the limiting criteria on skew, and then resynching (or reestablishing) the zero-skew condition at each repeater station. However, the use of repeater stations may be undesirable since they significantly add to the cost of the system.
Another prior art approach to the problem presented, typically utilized in signal modulation schemes, is to use a self-clocking or Manchester coding scheme for the data. In such a coding scheme, both the clock and data signals are multiplexed onto a single signal line, which thus contains both the data and data rate information. Thus, in a typical application, the signal makes one or two transitions per data bit period, with one transition indicating a binary zero and two transitions indicating a binary one. Since the self-clocking approach utilizes only one channel, there is no possibility for differential clock and data delays. The major drawback of the self-clocking scheme is that the single channel must have a larger capacity than the message rate. Typically, the channel must be capable of transmitting information at a rate at least twice the rate at which data is effectively transferred. Thus, in many situations it may be infeasible or much more expensive to provide one channel with a capacity of 2X rather than two channels each with a capacity of 1X. As a further disadvantage, the data separator (or demodulator) required to extract the data signal from the multiplexed clock/data signal is often expensive to implement.
In yet another approach to the problem, circuitry is provided to select one edge of the received clock signal to use to strobe the data, the selection being based on which edge is identified by the circuitry as being close to the center of the data cell. The circuitry employs a tapped delay line, whose input is the received data signal, to generate a timing window. The first clock edge (rising or falling) which occurs within the window is selected for use to strobe the data. If neither edge occurs within this window, one edge is arbitrarily selected. This approach suffers from the fact that under some within-specification values of clock frequency, clock asymmetry and data asymmetry, both edges of the clock signal could be too close to the edge of the data cell; viz, neither is usable. However, in such a case, since one clock edge is arbitrarily chosen if neither is within the generated timing window, it is possible to select and use an unusable clock edge. Although eliminating the default selection of one edge if neither occurs within the window would seem to be an acceptable modification to overcome this drawback, it in fact is not since it could result in the rejection of perfectly within-specification clock/data signals.